Floating trap type nonvolatile memory devices have generally the same structure as MOS transistors and use a multi-layered insulating layer as a gate insulating layer. The multi-layered insulating layer generally includes a tunnel insulating layer, a charge trap insulating layer, and a blocking insulating layer. Conventionally, the charge trap insulating layer is made of charge trapping material such as silicon nitride. In the floating trap type nonvolatile memory device, data is stored by injecting electrons into the charge trap insulating layer. This injection may be performed by a Fowler-Nordheim (F-N) tunneling mechanism or a hot carrier injection mechanism. Conversely, data may be erased by drawing electrons from the charge trap insulating layer or injecting holes into an electron storage layer.
Multi-bit memory cells provide a mass storage device without increasing physical dimensions. Most multi-bit memory cells use a multi-level threshold voltage to store two bits or more. In another type of multi-bit memory cell, two bits are stored on both sides (electron storage regions) of a floating trap type memory device, respectively. This structure has been disclosed in the technical article entitled “A NOVEL LOCALIZED TRAPPING, 2-BIT NONVOLATILE MEMORY CELL”, Boaz Eitan, Paolo Pavan, Ilan Bloom, Efraim Aloni, Aviv Frommer, and David Finzi, IEEE Electron Device Letters, Vol. 21, November 2000.
A top plan view of a conventional floating trap type multi-bit memory device is illustrated in FIG. 1, and a cross-sectional view taken along the line I-I′ of FIG. 1 is illustrated in FIG. 2.
In the conventional memory device, a plurality of bitline strips 10 cross a semiconductor substrate 20 in parallel. The bitline strips 10 may be buried diffusion layers where impurities are implanted into the substrate 20. A plurality of wordlines 12 cross the bitline strips 10. Each area between the bitlines strips 10 corresponds to a channel of a transistor. A tunnel insulating layer 14, a charge trap insulating layer 16, and a blocking insulating layer 18 are sequentially stacked between the channels and the wordlines 12 to form a multi-layered insulating layer. Conventionally, the multi-layered insulating layer is made of oxide-nitride-oxide (ONO). An intersection of a pair of adjacent bitline strips 10 and a wordline 12 corresponds to a memory cell. That is, a pair of the adjacent bitline strips 10, the wordline 12, the multi-layered insulating layer sandwiched between a wordline and a semiconductor substrate correspond to a source/drain region, a gate electrode, and a gate insulating layer, respectively. Two bits B1 and B2 are stored at both sides of the gate insulating layer, respectively.
In a memory cell of the conventional memory device, a right bit is written by using a left bitline as a source and a right bitline as a drain, while a left bit is written by using a right bitline as a source and a left bitline as a drain. If a ground voltage, a gate voltage of 10V or higher, and a write voltage of about 5V are applied to a left bitline, a gate electrode, and a right bitline respectively, electrons are trapped in a charge trap insulating layer at a junction of the right bitline due to hot carrier injection. Likewise, if a ground voltage and a write voltage are applied to the right bitline and the left bitline respectively, the left bit is written. In a read operation, the left bit is read out by applying a gate voltage of about 3V, a read voltage of about 2V, and a ground voltage to the gate electrode, the right bitline, and the left bitline, respectively. Likewise, the right bit is read out by applying a ground voltage and a read voltage to the right bitline and the left bitline, respectively.